The present invention generally relates to complimentary metal-oxide semiconductors (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFET), and more specifically, to contact formation during geometrically-scaled FET device fabrication.
The MOSFET is a transistor used for switching electronic signals. The finFET is a multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. Due to improved short channel effects, the finFET is a widely used form of geometrically-scaled FETs. The word “fin” refers to a generally fin-shaped semiconductor structure patterned on a substrate that often has three exposed surfaces that form the narrow channel between source and drain regions. A thin dielectric layer arranged over the fin separates the fin channel from the gate. Because the fin provides a three dimensional surface for the channel region, a larger channel length (gate width) can be achieved in a given region of the substrate as opposed to a planar FET device. However, geometrically-scaled FETs suffer from increased series, parasitic resistance. A large component of this parasitic resistance is the contact resistance between metallic interconnects and a semiconductor material of FET body. There is a continuous need for novel techniques and structures enabling lower contact resistance for geometrically-scaled FETs.